The need for efficient counter architecture has arisen for the following two reasons. Firstly, a number of data streaming algorithms and network management applications require a large number of counters in order to identify important traffic characteristics. And secondly, at high speeds, current memory devices have significant limitations in terms of speed (DRAM) and size (SRAM). For some applications no information on counters is needed on a per-packet basis and several methods have been

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... sed to handle this problem with low SRAM memory requirements. However, for a number of applications it is essential to have the counter information on every packet arrival. In this paper we propose two, computationally and memory efficient, randomized algorithms for approximating the counter values. We prove that proposed estimators are unbiased and give variance bounds. A case study on Multistage Filters (MSF) over the real Internet traces shows a significant improvement by using the active counters architecture. Index Terms-Counter architecture, high-speed measurements, router, data streaming algorithms. • full counters are stored in slow DRAM. • counters stored in DRAM are exact. In order to provide the exact values of DRAM counters 0743-166X/07/$25.00