Conductive interconnections through thick silicon substrates for 3D packaging

T. Takizawa, S. Yamamoto, K. Itoi, T. Suemasu
Technical Digest. MEMS 2002 IEEE International Conference. Fifteenth IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.02CH37266)  
We have developed key technologies to form conductive interconnections through a thick silicon substrate, which are potentially applied for 3D device fabrication or packaging of optical MEMS devices. In this paper, we demonstrate to form metal filled Through-Holes (THs) in thick Silicon (Si) substrates (t=~500µm) mainly using Photo Assisted Electro-Chemical Etching (PAECE)[1][2] and Molten Metal Suctioned Method (MMSM) [3] . The THs that we experimentally made with these technologies had 15µm
more » ... the diameter and the aspect ratio of 35. And the maximum density was 500THs/cm 2 . The dielectric breakdown voltage of the THs was more than 500V. In the result of a radioisotope leak test using Kr-85, the leakage rate of THs between the front and the back of the substrate was lower than the detection limit (1 X 10 -15 Pa•m 3 /sec.). Figure 9 Photograph of cross section of through-holes by PAECE with the backside mask shade (left), the 'peripheral effect' in fully opened backside (right).
doi:10.1109/memsys.2002.984284 fatcat:hvyxes7vr5bqnak6y42z4shmxm