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Vertical Test Reuse for Embedded Systems: A Systematic Mapping Study
2015
2015 41st Euromicro Conference on Software Engineering and Advanced Applications
Vertical test reuse refers to the the reuse of test cases or other test artifacts over different integration levels in the software or system engineering process. Vertical test reuse has previously been proposed for reducing test effort and improving test effectiveness, particularly for embedded system development. The goal of this study is to provide an overview of the state of the art in the field of vertical test reuse for embedded system development. For this purpose, a systematic mapping
doi:10.1109/seaa.2015.46
dblp:conf/euromicro/FlemstromSA15
fatcat:yec4qhncujblhgeipz3v7ktoiu