An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we present a network interface (NI) for an on-chip network. Our NI decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transactionbased protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP, and DTL. Our NI has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are
more » ... ed via NI ports using the network itself, instead of a separate control interconnect. An example instance of this NI with four ports has an area of 0.25 mm 2 after layout in 0.13-m technology, and runs at 500 MHz.
doi:10.1109/tcad.2004.839493 fatcat:4fyt7hueezehvnhc35tokrmrtq