Parallel Test Scheduling of 3D Stacked SoCs with Temperature and Time Constraints [dataset]

Iosr Journals, Indira Rawat, M.K. Gupta, Virendra Singh
2015 Figshare  
Today's VLSI circuits are very compact and complex designs. As the advancements made are very fast with cut throat competitions from various manufacturers, they are likely to have more defects and faults. This requires a proper testing process to be adopted for all products. Testing is a process which has to be done on all pieces of products. At the same time it requires a low cost, highly efficient method to be adopted. Fault coverage should also be maximized for ensuring fast and efficient
more » ... k. The technology is also undergoing fast transitions. System on Chip is a design paradigm which involves integration of entire system onto a single chip. It can be a RAM, DRAM, CPU, UDL, analog , digital, A/D or D/A converters needed for any particular requirement. In this paper we have worked on test scheduling of 3D SoCs with thermal and time constraints. The circuits used have been built using benchmark SoC circuits. They have been piled on top of each other to build two, three and four stack circuits. The method has been compared with the sequential method of testing. The method proposed in this work shows good thermal response and elimination of hotspots.
doi:10.6084/m9.figshare.1518539.v1 fatcat:ihr5zt5m6nb37g35iga7s6tly4