Reduction of Simultaneous Switching Noise in Digital Circuits

E. Backenius, M. Vesterbacka
2006 2006 NORCHIP  
In this paper we present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. We use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced
more » ... y 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.
doi:10.1109/norchp.2006.329207 fatcat:bxffbakz2bbrfnagruvoe36ksy