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PS-cache: an energy-efficient cache design for chip multiprocessors
2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
Repeated tree traversals are ubiquitous in many domains such as scientific simulation, data mining and graphics. Modern commodity processors support SIMD instructions, and using these instructions to process multiple traversals at once has the potential to provide substantial performance improvements. Unfortunately these algorithms often feature highly diverging traversals which inhibit efficient SIMD utilization, to the point that other, less profitable sources of vectorization must be
doi:10.1109/pact.2013.6618832
dblp:conf/IEEEpact/JoGK13
fatcat:7ek5mqgqk5dixlt4wuczu36ocq