3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor

K. Suresh Kumar, S. Anitha, M. Gayathri
2015 International Journal of Students Research in Technology & Management  
In this model a runtime cache data mapping is discussed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The suggested method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows energy reduction achieving up to 22.88% compared to an existing solution which considers only the temperature distribution. New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep
more » ... reasing the performance of the next-generation high performance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility.
doi:10.18510/ijsrtm.2015.325 fatcat:wxb36ypu2zfizmltie2xjqvxe4