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This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network -on-Chip) , targeted at future mobile systems. We suggest the architecture of the memory controller optimized to minimize synchronization overhead. The proposed solution is based on the idea of performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks), locally in the memory. Wedoi:10.1145/1147349.1147357 fatcat:glxyh2x3qbbodplpgu5icukz6q