A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit <a rel="external noopener" href="http://www.princeton.edu/~peh/publications/ptpolaris.pdf">the original URL</a>. The file type is <code>application/pdf</code>.
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature. Traditional methods of assuming a uniform temperature and no process variation can lead to gross inaccuracies even for system-level design, thus it is critical to consider the effects of process variation and temperature variation during early design exploration. In this paper, we describe the implementation of an architecture-level early-stage design<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/nocs.2008.4492731">doi:10.1109/nocs.2008.4492731</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/a76flhoklfdxbic6p7waqgsal4">fatcat:a76flhoklfdxbic6p7waqgsal4</a> </span>
more »... space exploration tool that incorporates the effect of process and temperature variation for Network-on-chips(NoC). The tool is used to study the impact of process and temperature variations on power and energy-delay-product-per-flit metrics for different NoC architectures, and our simulation results show that design choices are very much influenced by the effects of process and temperature variation, thus demonstrating the importance of considering, and enabling the highlevel impact analysis of process and temperature variation early in the design flow.
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