Design topology aware physical metrics for placement analysis

Shyam Ramji, Nagu R. Dhanwada
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
Traditionally placement evaluation metrics have been based on wirelength and congestion measures and are independent of the logic network topology. However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology. In this paper, we propose a designtopology aware metric that encapsulates the structural property of the circuit and physical goodness of the given placement. We present such a metric which is based on path monotonicity
more » ... an efficient method to compute this measure for a given placement. This method involves abstract path generation, clustering based region refinement and physical monotonicity analysis. Experimental results on real industry designs, using a commercial strength design closure flow, establish the usefulness of this metric in predicting the quality of a given placement with respect to design timing closure. Abstract Region 1 Abstract Region 2 Abstract Region 3 Merged Region (AbsPath2, AbsPath3)
doi:10.1145/764856.764857 fatcat:mtkin2mku5h4rl6yl7rxajnqdy