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Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03
Traditionally placement evaluation metrics have been based on wirelength and congestion measures and are independent of the logic network topology. However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology. In this paper, we propose a designtopology aware metric that encapsulates the structural property of the circuit and physical goodness of the given placement. We present such a metric which is based on path monotonicitydoi:10.1145/764856.764857 fatcat:mtkin2mku5h4rl6yl7rxajnqdy