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A floating-point accumulator for FPGA-based high performance computing applications
2009
2009 International Conference on Field-Programmable Technology
A floating-point accumulator for FPGA-based high performance computing applications is proposed and evaluated. Compared to previous work, our accumulator uses a fixed size circuit, and can reduce an arbitrary number of input sets of varying sizes without requiring prior knowledge of the bounds of summands. In this paper, we describe how the adder accumulator operator can be heavily pipelined to achieve a high clock speed when mapped to FPGA technology, while still maintaining the original input
doi:10.1109/fpt.2009.5377624
fatcat:pqbx74i6ina3dknxmu6mdtcwvq