Optimization of CMOS power-cell layout for improving junction breakdown

Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyoungsoo Kim, Joonhui Hur, Kiseok Yang, Kyutae Lim, Chang-Ho Lee, Joy Laskar
2014 IEICE Electronics Express  
Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-µm CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.
doi:10.1587/elex.11.20140523 fatcat:qs4wnftrkjfurh3dtmbucqs5z4