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A New System Design Methodology for Wire Pipelined SoC
Design, Automation and Test in Europe
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Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural changes are needed to preserve functionality. We illustrate a proposal that, while allowing the use of IP blocks without modification, takes advantage of a minimal knowledge of the IP's communication profile to dramatically increase the performances. We showed the formal equivalence between WP and original system and
doi:10.1109/date.2005.25
dblp:conf/date/CasuM05
fatcat:3xatfjm5gndija32fniiee2i5e