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Reduction of Substrate Noise in Sub Clock Frequency Range
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous Ddoi:10.1109/tcsi.2009.2031749 fatcat:ujwd4tfj3nb2fl6ej3zhlowbr4