Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

Aswini Valluri, Department of Electronics and communication Engineering, VFSTR, Vadlamudi, India, Sarada Musala, Muralidharan Jayabalan, Department of Electronics and communication Engineering, VFSTR, Vadlamudi, India, Departmentof Electronics and communication Engineering, KPR Institute of engineering and Technology, Coimbatore, India
2021 Maǧallaẗ al-abḥāṯ al-handasiyyaẗ  
There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It
more » ... s the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.
doi:10.36909/jer.10399 fatcat:xzwrfi5dtbfifonn7433dfvafa