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Low-leakage asymmetric-cell SRAM
Proceedings of the International Symposium on Low Power Electronics and Design
We introduce a novel family of asymmetric dualstatic random access memory cell designs that reduce leakage power in caches while maintaining low access latency. Our designs exploit the strong bias toward zero at the bit level exhibited by the memory value stream of ordinary programs. Compared to conventional symmetric high-performance cells, our cells offer significant leakage reduction in the zero state and, in some cases, also in the one state, albeit to a lesser extent. A novel sensedoi:10.1109/lpe.2002.1029518 fatcat:oantraiarfaofapoqeray6sohm