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Unified array architecture for discrete cosine transform, sine transform and their inverses
1995
Electronics Letters
Preserved Fulltext
area performance of the proposed array is O(Wlog,N) and the time performance is O(log,N). Thus, the resulting (area x time)' is O(W10g~~w, which is < O(Wlog,'N) achieved by the arrays in [8, 91. The features of high throughput performance and low areatime complexity make the proposed array useful for very high speed applications. It is also worth noting that the design for the I-D IDCT can be directly applied to evaluate the 2-D IDCT based on row-column decomposition.
doi:10.1049/el:19951254
fatcat:6a6lt4tgy5hohh23nn2g5akp5a