At-speed on-chip diagnosis of board-level interconnect faults

A. Jutman
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.  
This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults. The approach is based on a new parallel test pattern generator and a specific fault detecting sequence. The test sequence has tree major advantages. At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chip at-speed fault diagnosis of interconnect faults. Third, the hardware implementation of both the test generator and
more » ... response analyzer is very efficient in terms of silicon area.
doi:10.1109/etsym.2004.1347572 dblp:conf/ets/Jutman04 fatcat:iw7mqq535ra2fcjft7gbuejtlu