Two improved structures of high resolution digital pulse width modulator (DPWM) control circuit are proposed. Embedded digital clock manager (DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array (FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock

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... rates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides, the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability. Keywords: digital clock manager (DCM), digital programmable delay circuit, digital pulse width modulator (DPWM).