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A hardware architecture of Prewitt edge detection
2010
2010 IEEE Conference on Sustainable Utilization and Development in Engineering and Technology
The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge detection system. The architecture is capable of operating with a clock frequency of 145 MHz at 550 frames per second. Computation error analysis performed shows that the proposed architecture produces
doi:10.1109/student.2010.5686999
fatcat:nt5fzegsrbee7ajqpsdfcghrne