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Analysis of power consumption on switch fabrics in network routers
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress
doi:10.1109/dac.2002.1012681
fatcat:dfveqlvjrvc5tdxilit6vgflni