A Power-Efficient and Scalable Load-Store Queue Design [chapter]

Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
2005 Lecture Notes in Computer Science  
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor),
more » ... and only incurs a negligible performance loss of less than 0.6%.
doi:10.1007/11556930_1 fatcat:vad5cc4sgfhkxj4mfzjkf3lrze