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DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture
2016
2016 IEEE International Conference on Rebooting Computing (ICRC)
This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC²) concept based on memory architecture for data-intensive (imaging, ...) and secure (cryptography, ...) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed by an ALU. As a result, logic and arithmetic operations can be entirely executed within the
doi:10.1109/icrc.2016.7738698
dblp:conf/icrc/AkyelCMGSTN16
fatcat:ud2flsuy3rbjjahjn73b5m74sa