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Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair
Abstract| This article discusses the application of Pictorial Janus PJ for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we rst extend PJ by timing facilities Timed PJ and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We nally give the example of the specication and animation of a non interlocked protocol.doi:10.1109/aspdac.1995.486383 fatcat:jrtcynl53ngd5enhyy4fzi7ate