A highly efficient AES cipher chip

Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
We present an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0 25µm CMOS technology, the throughput rate is 2.977 Gbps for 128-bit keys, 2.510 Gbps for 192-bit keys, and 2.169 Gbps for 256bit keys
more » ... bps for 256bit keys with a 250MHz clock. Testability of the design is also considered. The area of the core circuit is about 1 279 ¢1 271µm 2 .
doi:10.1145/1119772.1119891 dblp:conf/aspdac/SuLHW03 fatcat:4qq35ybe6rcvndtggy4uhpyudi