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Flexible LDPC decoder architecture for high-throughput applications
2008
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
In this paper, we present a flexible highthroughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations. The proposed architecture is based on a block-parallel scheduling scheme using a layered
doi:10.1109/apccas.2008.4745956
dblp:conf/apccas/KimSL08
fatcat:p4zk6mwtg5ddffzs46nhi7loiu