Flexible LDPC decoder architecture for high-throughput applications

Sangmin Kim, Gerald E. Sobelman, Hanho Lee
2008 APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems  
In this paper, we present a flexible highthroughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations. The proposed architecture is based on a block-parallel scheduling scheme using a layered
more » ... ing method. To achieve higher throughput, check nodebased processes are implemented in a fully parallel architecture and the memory is partitioned into a number of banks. System flexibility is achieved by allowing the check node-based units and the memory banks to be configured according to the code rate and block size of the LDPC code of interest. I.
doi:10.1109/apccas.2008.4745956 dblp:conf/apccas/KimSL08 fatcat:p4zk6mwtg5ddffzs46nhi7loiu