Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Y.V. Ponomarev, C. Salm, J. Schmitz, P.H. Woerlee, P.A. Stolk, D.J. Gravesteijn
International Electron Devices Meeting. IEDM Technical Digest  
We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18pm devices are manufactured using p-and n-type poly-Si/Sio,8Geo.z gates.
doi:10.1109/iedm.1997.650509 fatcat:kbs23mpzxne25k5chmbvfuliam