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We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over , where m is the number of LFSR stages. The results indicatedoi:10.1145/1119772.1119963 dblp:conf/aspdac/IchinoWAFI03 fatcat:uojy34ghlzfnpaegsx3bwhxig4