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Fault Secure Encoder and Decoder with Clock Gating
2012
International Journal of VLSI Design & Communication Systems
This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to
doi:10.5121/vlsic.2012.3212
fatcat:h7oyr676lfhbdoa2sspmclmmfa