Fault Secure Encoder and Decoder with Clock Gating

N Kapileswar
2012 International Journal of VLSI Design & Communication Systems  
This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to
more » ... reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn't employ clock gating technique
doi:10.5121/vlsic.2012.3212 fatcat:h7oyr676lfhbdoa2sspmclmmfa