A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is
A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015 mm 2 . It operates over a frequency range of 2.0-4.0 GHz with a programmable frequency multiplication factordoi:10.1587/elex.13.20161056 fatcat:phi27imtefdrrixg22lkkulyla