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DRAM cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significantdoi:10.1109/hpca.2013.6522355 dblp:conf/hpca/NairCQ13 fatcat:mdxxxpqkh5cktbhgkzlfsl2m2y