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Clock distribution networks (CDNs) are costly in high-performance ASICs. This paper proposes a new approach: splitting clock domains at a very fine level, down to the level of a handful of gates. Each domain is synchronized with an inexpensive clock signal, generated locally. This is possible by adopting the paradigm of stochastic computation, where signal values are encoded as random bit streams. The design method is illustrated with the synthesis of circuits for applications in signal and image processing.doi:10.1109/aspdac.2016.7428060 dblp:conf/aspdac/NajafiLRB16 fatcat:hwthozrvfveprijyj3q7a4cdda