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Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performancedoi:10.1145/360128.360153 fatcat:rlmk5hj2bveeva22wpnkvzmla4