Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC
IJARCCE - Computer and Communication Engineering

A. LAKSHMINARAYANAN, N. JAYAPAL, R. SHANKAR, D. KARTHIKEYAN
2014 IJARCCE  
An extremely low-power flip-flop named topologically-compressed flip-flop is planned. As compared with standard FFs, the FF reduces power dissipation by seventy fifth at 1/3 information activity. This power reduction magnitude relation is that the highest among FFs that are reported thus far. The reduction is achieved by applying topological compression methodology, merger of logically equivalent transistors to associate unconventional latch structure. The terribly little variety of
more » ... iety of transistors, only three, connected to clock signal reduces the facility drastically, and therefore the smaller total transistor count assures identical cell space as standard FFs. In addition, absolutely static full-swing operation makes the cell tolerant of provide voltage and input slew variation. associate experimental chip design with forty nm CMOS technology shows that nearly all standard FFs are replaceable with planned FF whereas protective the same system performance and layout space.
doi:10.17148/ijarcce.2014.31152 fatcat:vtfxzmufxvhxtek5gpl6chgnga