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Phase-locking in wireline systems: Present and future
2008
2008 IEEE Custom Integrated Circuits Conference
This paper describes the challenges in the design of phaselocked loops and clock and data recovery circuits as speeds approach 80-100 Gb/s. Skew and jitter issues are presented and the effect of reference phase noise, charge pump noise, reference spurs, and loop filter leakage is quantified. The phase noise performance of cascaded loops is analyzed and two new architectures are proposed.
doi:10.1109/cicc.2008.4672162
dblp:conf/cicc/Razavi08
fatcat:2rixwdwhjbd2ffed32dr6tvtea