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Modeling of a multi-core microblaze system at RTL and TLM abstraction levels in systemC
Transaction Level Modeling (TLM) has recently become a popular approach for modeling contemporary Systems-on-Chip (SoCs) on a higher abstraction level than Register Transfer Level (RTL). In this thesis a multi-core system based on the Xilinx MicroBlaze micro-processor is modeled at RTL and TLM abstraction levels in SystemC. Both implemented models have cycle accurate timing, and are verified against the reference VHDL model using a VHDL / SystemC mixed-language simulation with ModelSim.doi:10.18419/opus-3067 fatcat:ku7lavdd6bbl3o457wfg6x7qda