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What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
2019
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Designing the hardware of a processor core as well as its verification flow from a single high-level specification would provide great advantages in terms of productivity and maintainability. In this work, we highlight the gain of starting from a unique high-level synthesis and simulation C++ model to design a processor core implementing the RISC-V Instruction Set Architecture (ISA). The specification code is used to generate both the hardware target design through High-Level Synthesis as well
doi:10.1109/iccad45719.2019.8942177
dblp:conf/iccad/RokickiPPS19
fatcat:jsjhpzki4fdjho6vqmpeb5hlxa