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Static extraction of memory access profiles for multi-core interference analysis of real-time tasks
[article]
2021
arXiv
pre-print
We present a static analysis framework for real-time task systems running on multi-core processors. Our method analyzes tasks in isolation at the binary level and generates worst-case timing and memory access profiles. These profiles can then be combined to perform an interference analysis at the task system level, as part of a multi-core Worst-Case Response Time (WCRT) analysis. In this paper we introduce a formal description of the models and algorithmic building blocks composing our
arXiv:2103.17082v1
fatcat:kw4b2sqi7vfnbdm6bhf4ujpcjm