A mixed-signal ASIC for the silicon drift detectors of the ALICE experiment in a $0.25\mu m$ CMOS [article]

Pierre Jarron, G Anelli, Francis Anghinolfi, G Mazza, A Rivetti
A mixed−signal integrated circuit developed for the front−end of the Silicon Drift Detectors (SDDs) is presented. The chip contains 32 channels and 16 analogue to digital converters. Each channel is made of an amplifier and an analogue pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit has been optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated
more » ... oise is calculated to be 200 e − rms for a total input capacitance of 3 pF and a detector leakage current of 10 nA. The average power consumption is 4 mW per channel.
doi:10.5170/cern-2000-010.142 fatcat:o4k7wgfky5g2tao7tkt2pe7cpa