Design and optimization of dual-threshold circuits for low-voltage low-power applications

L. Wei, Z. Chen, K. Roy, M.C. Johnson, Y. Ye, V.K. De
1999 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, 1 we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal
more » ... optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low-and high-switching activities, respectively.
doi:10.1109/92.748196 fatcat:rileg74qdbhwnbbkl5ynui434q