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Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, 1 we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimaldoi:10.1109/92.748196 fatcat:rileg74qdbhwnbbkl5ynui434q