A highly parallel Turbo Product Code decoder without interleaving resource

Camille Leroux, Christophe Jego, Patrick Adde, Michel Jezequel, Deepak Gupta
2008 2008 IEEE Workshop on Signal Processing Systems  
This article presents an innovative Turbo Product Code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26) 2 BCH product code, synthetized in a 90nm CMOS technology, the resulting information throughput is 2.5Gb/s with an area of
more » ... 233Kgates. Finally a second architecture enhancing parallelism rate is described. The information throughput is 33.7Gb/s while an area estimation gives A =10µm 2 .
doi:10.1109/sips.2008.4671728 dblp:conf/sips/LerouxJAJG08 fatcat:wdhhflodljb6jgvlqhui7yil7a