Latched differential FET logic

S.W. Wood, K.C. Smith, P.G. Gulak
1991., IEEE International Sympoisum on Circuits and Systems  
In this paper, we propose a new circuit topology for creating complex logic circuits in GaAs. Latched Differential FET Logic (LDFL) is a fully differential logic family that provides complex logic function capability, tolerance to threshold voltage variations and complementary, latched-function outputs. LDFL is capable of performing up to eleven levels of logic in one gate, while still giving excellent performance. LDFL also provides improved noise margins due to the use of bootstrapped loads
more » ... d significantly reduces the load-blogic ratioing constraint. A nine-level LDFL gate has a delay of 1.7ns and a static power dissipation of 4mW as demonstrated in simulations of Cbit digital comparator circuits.
doi:10.1109/iscas.1991.176179 fatcat:nro627ecerhaljwjpn7j6kowri