Boosters for driving long on-chip interconnects

Ankireddy Nalamalpu, Wayne Burleson
2001 Proceedings of the 2001 international symposium on Physical design - ISPD '01  
Trends in CMOS technology and VLSI architectures are causing interconnect to play an increasing role in overall performance, power consumption and design e ort. Traditionally, repeaters are used for driving long on-chip interconnects, however recent studies indicate that repeaters are using increasing area, power, and design resources as well as having an inherent limit in how m uch they can improve performance 4,10,14]. This paper presents a new circuit called a booster which compares
more » ... with repeaters in terms of area, performance, power and placement s e n s itivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are slower and peak power is drastically reduced compared to repeaters, thus improving signal integrity and mitigating inductive e e c t s . Boosters are shown to be more than 20% faster for driving a v ariety o f interconnect loads over conventional repeaters in 0.16 m CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths thereby s a ving on area, power and placement e ort. Unlike di erential, dynamic or low-swing techniques which require signi cantly more sophisticated circuit design and hence are cumbersome for automatic interconnect synthesis tools, boosters can be inserted on lines in a straightforward manner. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into a CAD tool. We formulate two design rules that determine 1) the number of boosters needed, 2) their placements and 3) sizes, for driving a given interconnect load, rst minimizing delay, and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement s e n s i -Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. tivity analysis comparing boosters and repeaters is used to study the e ects realistic placement constraints that arise in oor-plans. We conclude by discussing various design trade-o 's between repeater and booster based interconnect designs. Circuit simulations using a 0.16 m CMOS technology are used to verify all analytical results.
doi:10.1145/369691.369775 dblp:conf/ispd/NalamalpuB01 fatcat:6c4uk77vxrf2jhcnog5gkzxeqe