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This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This Application-Specific Instruction-set Processor has an SIMD architecture with a specialized and extensible instruction-set and 5-stages pipeline control. The attached memories and communication interfaces enable the design of efficient multiprocessor architectures. Thesedoi:10.1109/date.2006.244126 dblp:conf/date/MullerBJ06 fatcat:7a6wiaw2nveuvflvmhuao4bvei