A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
DESIGN OF POWER AND DELAY EFFICIENT 32 BIT X 32 BIT MULTI-PRECISION MULTIPLIER WITH OPERANDS SCHEDULER
2015
International Journal of Research in Engineering and Technology
Multipliers perform the most frequently encountered arithmetic operations in DSP applications. The proposed multi precision(MP) multiplier that incorporates variable precision, parallel processing (PP), and dedicated MP operands scheduling to provide optimum performance for a various operating conditions. The building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or it also work parallel to form higher-precision multipliers. To
doi:10.15623/ijret.2015.0402082
fatcat:5s63hf7ad5ghnnealw53wq4d5m