DESIGN OF POWER AND DELAY EFFICIENT 32 BIT X 32 BIT MULTI-PRECISION MULTIPLIER WITH OPERANDS SCHEDULER

Jitha K T .
2015 International Journal of Research in Engineering and Technology  
Multipliers perform the most frequently encountered arithmetic operations in DSP applications. The proposed multi precision(MP) multiplier that incorporates variable precision, parallel processing (PP), and dedicated MP operands scheduling to provide optimum performance for a various operating conditions. The building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or it also work parallel to form higher-precision multipliers. To
more » ... ce power consumption and delay, replaces the razor flip flop and voltage scaling unit .The Look up table (LUT) together with dynamic voltage and frequency management system configure the multiplier to work at low power consumption. The LUT stores the minimum voltages required for the multiplication of 8-bit, 16-bit and 32-bit multiplications. The multiplier consists of carry propagation adder which is replaced by carry select adder due to this a considerable delay reduction can be achieved. The MP multiplier is also consists of Frequency management unit makes the multiplier to operate at proper frequency. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, that determine the optimum voltage and frequency operating conditions for minimum power consumption. Experimental results show that the proposed MP Multiplier provides a 14.55% reduction in power consumption and 9.67% reduction in delay compared with conventional razor based DVS MP Multiplier. When combining this MP design with LUT, Parallel processing, and the operands scheduler, delay and power reduction can be achieved to a great extent. This paper successfully demonstrates that MP multiplier architecture can allow more aggressive frequency/supply voltage scaling for improved power and delay efficiency.
doi:10.15623/ijret.2015.0402082 fatcat:5s63hf7ad5ghnnealw53wq4d5m