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In order to provide dynamic adaptation of the performance/energy trade-off, systems today rely on heterogeneous multi-core architectures (different micro-architectures on a chip). These systems are limited to single-ISA approaches to enable transparent migration between the different cores. To offer more trade-off, we can integrate statically scheduled microarchitecture and use Dynamic Binary Translation (DBT) for task migration. However, in a system where performance and energy consumption aredoi:10.1109/tcad.2018.2864288 fatcat:a2axpoyilrajlmxujmtwwxll7q