Analysis of error detection schemes: Toolchain support and hardware/software implications

Ali Azarian, Joao Canas Ferreira, Stephan Werner, Zlatko Petrov, Joao M. P. Cardoso, Michael Huebner
2012 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
Meeting safety requirements typically require substantial invasive extensions to applications. Even in the absence of faults, the overhead associated with these invasive extensions may unacceptably increase execution time. In this paper we focus on a number of experiments with schemes for error detection, having a 3D Path Planning application for an avionics system as case study. We analyze how these error detection schemes can be implemented to meeting system's time budget. The experiments
more » ... The experiments allowed us to acquire the requirements for automating the application of the error detection schemes in the context of a hardware/software design-flow, and to determine how those schemes can be addressed using a novel approach where safety requirements are described using an aspect-and strategy-oriented programming language, named LARA. For our experiments and validation, we consider an FPGA-based embedded system consisting of a general purpose processor (GPP) coupled to custom computing units which are primarily used for hardware acceleration and for implementing fault detection schemes.
doi:10.1109/ahs.2012.6268670 dblp:conf/ahs/AzarianFWPCH12 fatcat:umdfkjkqfvgcpdtwfqsal4y75e