Parallel algorithms for FPGA placement

Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee
2000 Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00  
Fast FPGA CAD tools that produce high quality results has been one o] the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement ]or FPGA. We present experimental results obtained by applying the different parallelization strategies to the
more » ... n strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.
doi:10.1145/330855.330988 dblp:conf/glvlsi/HaldarNCB00 fatcat:ghg66d252vagdg42kloglzfrsy