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Fast FPGA CAD tools that produce high quality results has been one o] the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement ]or FPGA. We present experimental results obtained by applying the different parallelization strategies to thedoi:10.1145/330855.330988 dblp:conf/glvlsi/HaldarNCB00 fatcat:ghg66d252vagdg42kloglzfrsy