Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Monica Mankar, Gajendra Asutkar, Pravin Dakhole
<span title="2016-12-30">2016</span> <i title="Academy and Industry Research Collaboration Center (AIRCC)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dpfavoemqbeinduj3yjynh557i" style="color: black;">International Journal of VLSI Design &amp; Communication Systems</a> </i> &nbsp;
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower-triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of
more &raquo; ... C encoder will be compatible for high-speed applications. This hardwired architecture is less complex as it avoids conventionally used block memories and cyclic-shifters.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5121/vlsic.2016.7604">doi:10.5121/vlsic.2016.7604</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xslppi6xkzc3vp6stsjjmdqckm">fatcat:xslppi6xkzc3vp6stsjjmdqckm</a> </span>
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